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Data Sheet
Rev.1.2
09.11.2010
EEPROM using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes
This Swissbit module is an industry standard 200-pin 8-byte DDR2 SDRAM Small Outline Dual-In-line Memory
Module (SO-DIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally
configured octal-bank DDR2 SDRAM devices. The module uses double data rate architecture to achieve high-
speed operation. DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE
accesses to a DDR2 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power- saving “power - down” mode. All
inputs and all full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the optional serial presence detect (SPD) function implemented via serial
2
are utilized by the SO- DIMM manufacturer (swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
DDR2 SDRAMs used
Row
Device Bank
Column
Refresh
Module
Addr.
Addr.
Addr.
Bank Select
128M x 64bit
8 x 128M x 8bit (1024Mbit)
14
BA0, BA1,BA2
10
8k
S0#
Module Dimensions
in mm
67.60 (long) x 30 (high) x 3.80 [max] (thickness)
Timing Parameters
Part Number
SEN01G64D1BF1SA-25[E/W]R
SEN01G64D1BF1SA-30[E/W]R
Module Density
1024 MB
1024 MB
Transfer Rate
6.4 GB/s
5.3 GB/s
Clock Cycle/Data bit rate
2.5ns/800MT/s
3.0ns/667MT/s
Latency
6-6-6
5-5-5
Pin Name
A0-9, A11 – A13
A10/AP
BA0 – BA2
DQ0 – DQ63
DM0-DM7
DQS0 - DQS7
DQS0# - DQS7#
RAS#
CAS#
WE#
CKE0
CK0 – CK1
Swissbit AG
Address Inputs
Address Input / Autoprecharge Bit
Bank Address Inputs
Data Input / Output
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Inputs, positive line
Industriestrasse 4
Ch-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
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